/*
 * 
 * SYNTIANT CONFIDENTIAL
 * _____________________
 *  
 *   Copyright (c) 2018 Syntiant Corporation
 *   All Rights Reserved.
 *  
 *  NOTICE:  All information contained herein is, and remains the property of
 *  Syntiant Corporation and its suppliers, if any.  The intellectual and
 *  technical concepts contained herein are proprietary to Syntiant Corporation
 *  and its suppliers and may be covered by U.S. and Foreign Patents, patents in
 *  process, and are protected by trade secret or copyright law.  Dissemination
 *  of this information or reproduction of this material is strictly forbidden
 *  unless prior written permission is obtained from Syntiant Corporation.
 	** SDK: v110 **
*/
/*
 * ******* Automatically generated for ndp120_dnn v2.01  DO NOT MODIFY!!!!!
 *          Generated Fri Jan 22 19:37:45 2021 UTC
 */
#ifndef NDP120_DNN_REGS_H
#define NDP120_DNN_REGS_H

/*
 * block ndp120_dnn.isa, base 0x60080000
 */
#define NDP120_DNN_ISA 0x60080000U
#define NDP120_DNN_ISA_SIZE 0x00001000U
/* register ndp120_dnn.isa.comp0 */
#define NDP120_DNN_ISA_COMP0 0x60080000U
#define NDP120_DNN_ISA_COMP0_TYPE_SHIFT 0
#define NDP120_DNN_ISA_COMP0_TYPE_MASK 0x00000007U
#define NDP120_DNN_ISA_COMP0_TYPE(v) \
        ((v) << NDP120_DNN_ISA_COMP0_TYPE_SHIFT)
#define NDP120_DNN_ISA_COMP0_TYPE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_TYPE_SHIFT))
#define NDP120_DNN_ISA_COMP0_TYPE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_TYPE_MASK) | ((v) << NDP120_DNN_ISA_COMP0_TYPE_SHIFT))
#define NDP120_DNN_ISA_COMP0_TYPE_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_TYPE_MASK) >> NDP120_DNN_ISA_COMP0_TYPE_SHIFT)
#define NDP120_DNN_ISA_COMP0_TYPE_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_TYPE_FULL_CONN 0x0U
#define NDP120_DNN_ISA_COMP0_TYPE_CONV 0x1U
#define NDP120_DNN_ISA_COMP0_TYPE_CONV_DW 0x2U
#define NDP120_DNN_ISA_COMP0_TYPE_DECONV 0x3U
#define NDP120_DNN_ISA_COMP0_TYPE_AVG_POOL 0x4U
#define NDP120_DNN_ISA_COMP0_TYPE_MAX_POOL 0x5U
#define NDP120_DNN_ISA_COMP0_TYPE_MAX 0x5U
#define NDP120_DNN_ISA_COMP0_TYPE_VALID(v) \
        (v >= 0 && v <= 5)
#define NDP120_DNN_ISA_COMP0_ACTIVATION_SHIFT 3
#define NDP120_DNN_ISA_COMP0_ACTIVATION_MASK 0x00000038U
#define NDP120_DNN_ISA_COMP0_ACTIVATION(v) \
        ((v) << NDP120_DNN_ISA_COMP0_ACTIVATION_SHIFT)
#define NDP120_DNN_ISA_COMP0_ACTIVATION_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_ACTIVATION_SHIFT))
#define NDP120_DNN_ISA_COMP0_ACTIVATION_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_ACTIVATION_MASK) | ((v) << NDP120_DNN_ISA_COMP0_ACTIVATION_SHIFT))
#define NDP120_DNN_ISA_COMP0_ACTIVATION_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_ACTIVATION_MASK) >> NDP120_DNN_ISA_COMP0_ACTIVATION_SHIFT)
#define NDP120_DNN_ISA_COMP0_ACTIVATION_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_LINEAR 0x0U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_LINEAR_16 0x1U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_RELU 0x2U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_TANH0 0x4U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_TANH1 0x5U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_SIGMOID0 0x6U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_SIGMOID1 0x7U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_MAX 0x7U
#define NDP120_DNN_ISA_COMP0_ACTIVATION_VALID(v) \
        (v == NDP120_DNN_ISA_COMP0_ACTIVATION_LINEAR || v == NDP120_DNN_ISA_COMP0_ACTIVATION_LINEAR_16 || v == NDP120_DNN_ISA_COMP0_ACTIVATION_RELU || v == NDP120_DNN_ISA_COMP0_ACTIVATION_TANH0 || v == NDP120_DNN_ISA_COMP0_ACTIVATION_TANH1 || v == NDP120_DNN_ISA_COMP0_ACTIVATION_SIGMOID0 || v == NDP120_DNN_ISA_COMP0_ACTIVATION_SIGMOID1)
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_SHIFT 6
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_MASK 0x000000c0U
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE(v) \
        ((v) << NDP120_DNN_ISA_COMP0_INPUT_TYPE_SHIFT)
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_INPUT_TYPE_SHIFT))
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_INPUT_TYPE_MASK) | ((v) << NDP120_DNN_ISA_COMP0_INPUT_TYPE_SHIFT))
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_INPUT_TYPE_MASK) >> NDP120_DNN_ISA_COMP0_INPUT_TYPE_SHIFT)
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_UNSIGNED8 0x0U
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_SIGNED8 0x1U
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_SIGNED16 0x2U
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_MAX 0x2U
#define NDP120_DNN_ISA_COMP0_INPUT_TYPE_VALID(v) \
        (v >= 0 && v <= 2)
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_SHIFT 8
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_MASK 0x00000700U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH(v) \
        ((v) << NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_SHIFT)
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_SHIFT))
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_MASK) | ((v) << NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_SHIFT))
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_MASK) >> NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_SHIFT)
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_BIT1 0x0U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_BIT2 0x1U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_BIT4 0x2U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_BIT8 0x3U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_BIT4Q 0x4U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_BIT4SH 0x5U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_MAX 0x5U
#define NDP120_DNN_ISA_COMP0_WEIGHTS_WIDTH_VALID(v) \
        (v >= 0 && v <= 5)
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SHIFT 11
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MASK 0x00003800U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE(v) \
        ((v) << NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SHIFT)
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SHIFT))
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MASK) | ((v) << NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SHIFT))
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MASK) >> NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SHIFT)
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_NO_SB 0x0U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MULTI_SB 0x4U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MULTI_S_SINGLE_B 0x5U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SINGLE_S_MULTI_B 0x6U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SINGLE_SB 0x7U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MAX 0x7U
#define NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_VALID(v) \
        (v == NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_NO_SB || v == NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MULTI_SB || v == NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_MULTI_S_SINGLE_B || v == NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SINGLE_S_MULTI_B || v == NDP120_DNN_ISA_COMP0_SCALE_BIAS_TYPE_SINGLE_SB)
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_SHIFT 14
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_MASK 0x00004000U
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION(v) \
        ((v) << NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_SHIFT)
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_SHIFT))
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_MASK) | ((v) << NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_SHIFT))
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_MASK) >> NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_SHIFT)
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_STRIDE 0x0U
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_DILATION 0x1U
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_MAX 0x1U
#define NDP120_DNN_ISA_COMP0_SELECT_STRIDE_DILATION_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_DNN_ISA_COMP0_INTERRUPT_SHIFT 15
#define NDP120_DNN_ISA_COMP0_INTERRUPT_MASK 0x007f8000U
#define NDP120_DNN_ISA_COMP0_INTERRUPT(v) \
        ((v) << NDP120_DNN_ISA_COMP0_INTERRUPT_SHIFT)
#define NDP120_DNN_ISA_COMP0_INTERRUPT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_INTERRUPT_SHIFT))
#define NDP120_DNN_ISA_COMP0_INTERRUPT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_INTERRUPT_MASK) | ((v) << NDP120_DNN_ISA_COMP0_INTERRUPT_SHIFT))
#define NDP120_DNN_ISA_COMP0_INTERRUPT_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_INTERRUPT_MASK) >> NDP120_DNN_ISA_COMP0_INTERRUPT_SHIFT)
#define NDP120_DNN_ISA_COMP0_INTERRUPT_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_POINTER_SHIFT 23
#define NDP120_DNN_ISA_COMP0_POINTER_MASK 0x7f800000U
#define NDP120_DNN_ISA_COMP0_POINTER(v) \
        ((v) << NDP120_DNN_ISA_COMP0_POINTER_SHIFT)
#define NDP120_DNN_ISA_COMP0_POINTER_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_POINTER_SHIFT))
#define NDP120_DNN_ISA_COMP0_POINTER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_POINTER_MASK) | ((v) << NDP120_DNN_ISA_COMP0_POINTER_SHIFT))
#define NDP120_DNN_ISA_COMP0_POINTER_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_POINTER_MASK) >> NDP120_DNN_ISA_COMP0_POINTER_SHIFT)
#define NDP120_DNN_ISA_COMP0_POINTER_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_STOP_SHIFT 31
#define NDP120_DNN_ISA_COMP0_STOP_MASK 0x80000000U
#define NDP120_DNN_ISA_COMP0_STOP(v) \
        ((v) << NDP120_DNN_ISA_COMP0_STOP_SHIFT)
#define NDP120_DNN_ISA_COMP0_STOP_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP0_STOP_SHIFT))
#define NDP120_DNN_ISA_COMP0_STOP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP0_STOP_MASK) | ((v) << NDP120_DNN_ISA_COMP0_STOP_SHIFT))
#define NDP120_DNN_ISA_COMP0_STOP_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP0_STOP_MASK) >> NDP120_DNN_ISA_COMP0_STOP_SHIFT)
#define NDP120_DNN_ISA_COMP0_STOP_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP0_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp1 */
#define NDP120_DNN_ISA_COMP1 0x60080004U
#define NDP120_DNN_ISA_COMP1_BANK_IN_SHIFT 0
#define NDP120_DNN_ISA_COMP1_BANK_IN_MASK 0x00000001U
#define NDP120_DNN_ISA_COMP1_BANK_IN(v) \
        ((v) << NDP120_DNN_ISA_COMP1_BANK_IN_SHIFT)
#define NDP120_DNN_ISA_COMP1_BANK_IN_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP1_BANK_IN_SHIFT))
#define NDP120_DNN_ISA_COMP1_BANK_IN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP1_BANK_IN_MASK) | ((v) << NDP120_DNN_ISA_COMP1_BANK_IN_SHIFT))
#define NDP120_DNN_ISA_COMP1_BANK_IN_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP1_BANK_IN_MASK) >> NDP120_DNN_ISA_COMP1_BANK_IN_SHIFT)
#define NDP120_DNN_ISA_COMP1_BANK_IN_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP1_BANK_IN_MEM_BANK0 0x0U
#define NDP120_DNN_ISA_COMP1_BANK_IN_MEM_BANK1 0x1U
#define NDP120_DNN_ISA_COMP1_BANK_IN_MAX 0x1U
#define NDP120_DNN_ISA_COMP1_BANK_IN_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_SHIFT 1
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_MASK 0x0007fffeU
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD(v) \
        ((v) << NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_SHIFT)
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_SHIFT))
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_MASK) | ((v) << NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_SHIFT))
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_MASK) >> NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_SHIFT)
#define NDP120_DNN_ISA_COMP1_INPUT_BASE_COORD_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET_SHIFT 19
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET_MASK 0x7ff80000U
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET(v) \
        ((v) << NDP120_DNN_ISA_COMP1_INPUT_OFFSET_SHIFT)
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP1_INPUT_OFFSET_SHIFT))
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP1_INPUT_OFFSET_MASK) | ((v) << NDP120_DNN_ISA_COMP1_INPUT_OFFSET_SHIFT))
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP1_INPUT_OFFSET_MASK) >> NDP120_DNN_ISA_COMP1_INPUT_OFFSET_SHIFT)
#define NDP120_DNN_ISA_COMP1_INPUT_OFFSET_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_SHIFT 31
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_MASK 0x80000000U
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB(v) \
        ((v) << NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_MASK) | ((v) << NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_MASK) >> NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP1_INPUT_SIZE0_LSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP1_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp2 */
#define NDP120_DNN_ISA_COMP2 0x60080008U
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_SHIFT 0
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_MASK 0x000007ffU
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB(v) \
        ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_MASK) | ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_MASK) >> NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE0_MSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1_SHIFT 11
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1_MASK 0x007ff800U
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1(v) \
        ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE1_SHIFT)
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE1_SHIFT))
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP2_INPUT_SIZE1_MASK) | ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE1_SHIFT))
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP2_INPUT_SIZE1_MASK) >> NDP120_DNN_ISA_COMP2_INPUT_SIZE1_SHIFT)
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE1_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_SHIFT 23
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_MASK 0xff800000U
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB(v) \
        ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_MASK) | ((v) << NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_MASK) >> NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP2_INPUT_SIZE2_LSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP2_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp3 */
#define NDP120_DNN_ISA_COMP3 0x6008000cU
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_SHIFT 0
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_MASK 0x00000007U
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB(v) \
        ((v) << NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_MASK) | ((v) << NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_MASK) >> NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP3_INPUT_SIZE2_MSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP3_BANK_OUT_SHIFT 3
#define NDP120_DNN_ISA_COMP3_BANK_OUT_MASK 0x00000008U
#define NDP120_DNN_ISA_COMP3_BANK_OUT(v) \
        ((v) << NDP120_DNN_ISA_COMP3_BANK_OUT_SHIFT)
#define NDP120_DNN_ISA_COMP3_BANK_OUT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP3_BANK_OUT_SHIFT))
#define NDP120_DNN_ISA_COMP3_BANK_OUT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP3_BANK_OUT_MASK) | ((v) << NDP120_DNN_ISA_COMP3_BANK_OUT_SHIFT))
#define NDP120_DNN_ISA_COMP3_BANK_OUT_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP3_BANK_OUT_MASK) >> NDP120_DNN_ISA_COMP3_BANK_OUT_SHIFT)
#define NDP120_DNN_ISA_COMP3_BANK_OUT_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP3_BANK_OUT_MEM_BANK0 0x0U
#define NDP120_DNN_ISA_COMP3_BANK_OUT_MEM_BANK1 0x1U
#define NDP120_DNN_ISA_COMP3_BANK_OUT_MAX 0x1U
#define NDP120_DNN_ISA_COMP3_BANK_OUT_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_SHIFT 4
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_MASK 0x003ffff0U
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD(v) \
        ((v) << NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_SHIFT)
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_SHIFT))
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_MASK) | ((v) << NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_SHIFT))
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_MASK) >> NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_SHIFT)
#define NDP120_DNN_ISA_COMP3_OUTPUT_BASE_COORD_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_SHIFT 22
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_MASK 0xffc00000U
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB(v) \
        ((v) << NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_MASK) | ((v) << NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_MASK) >> NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP3_OUTPUT_SIZE0_LSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP3_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp4 */
#define NDP120_DNN_ISA_COMP4 0x60080010U
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_SHIFT 0
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_MASK 0x00000003U
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB(v) \
        ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_MASK) | ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_MASK) >> NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE0_MSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_SHIFT 2
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_MASK 0x00003ffcU
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1(v) \
        ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_SHIFT)
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_SHIFT))
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_MASK) | ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_SHIFT))
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_MASK) >> NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_SHIFT)
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE1_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_SHIFT 14
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_MASK 0x03ffc000U
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2(v) \
        ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_SHIFT)
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_SHIFT))
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_MASK) | ((v) << NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_SHIFT))
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_MASK) >> NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_SHIFT)
#define NDP120_DNN_ISA_COMP4_OUTPUT_SIZE2_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_SHIFT 26
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_MASK 0xfc000000U
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB(v) \
        ((v) << NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_MASK) | ((v) << NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_MASK) >> NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP4_NUM_FILTERS_LSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP4_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp5 */
#define NDP120_DNN_ISA_COMP5 0x60080014U
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_SHIFT 0
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_MASK 0x0000003fU
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB(v) \
        ((v) << NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_MASK) | ((v) << NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_MASK) >> NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP5_NUM_FILTERS_MSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_SHIFT 6
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_MASK 0x001fffc0U
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR(v) \
        ((v) << NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_SHIFT)
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_SHIFT))
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_MASK) | ((v) << NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_SHIFT))
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_MASK) >> NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_SHIFT)
#define NDP120_DNN_ISA_COMP5_WEIGHTS_BASE_ADDR_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_SHIFT 21
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_MASK 0xffe00000U
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB(v) \
        ((v) << NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_MASK) | ((v) << NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_MASK) >> NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP5_SCALER_BASE_ADDR_LSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP5_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp6 */
#define NDP120_DNN_ISA_COMP6 0x60080018U
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_SHIFT 0
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_MASK 0x0000000fU
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB(v) \
        ((v) << NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_MASK) | ((v) << NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_MASK) >> NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP6_SCALER_BASE_ADDR_MSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_SHIFT 4
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_MASK 0x000003f0U
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0(v) \
        ((v) << NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_SHIFT)
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_SHIFT))
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_MASK) | ((v) << NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_SHIFT))
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_MASK) >> NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_SHIFT)
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING0_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_SHIFT 10
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_MASK 0x0000fc00U
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1(v) \
        ((v) << NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_SHIFT)
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_SHIFT))
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_MASK) | ((v) << NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_SHIFT))
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_MASK) >> NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_SHIFT)
#define NDP120_DNN_ISA_COMP6_KERNEL_POOLING1_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_SHIFT 16
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_MASK 0x003f0000U
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0(v) \
        ((v) << NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_SHIFT)
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_SHIFT))
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_MASK) | ((v) << NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_SHIFT))
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_MASK) >> NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_SHIFT)
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION0_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_SHIFT 22
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_MASK 0x0fc00000U
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1(v) \
        ((v) << NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_SHIFT)
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_SHIFT))
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_MASK) | ((v) << NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_SHIFT))
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_MASK) >> NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_SHIFT)
#define NDP120_DNN_ISA_COMP6_STRIDE_DILATION1_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_SHIFT 28
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_MASK 0xf0000000U
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB(v) \
        ((v) << NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_MASK) | ((v) << NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_SHIFT))
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_MASK) >> NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_SHIFT)
#define NDP120_DNN_ISA_COMP6_PADDING_SIZE0_LSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP6_DEFAULT 0x00000000U 
/* register ndp120_dnn.isa.comp7 */
#define NDP120_DNN_ISA_COMP7 0x6008001cU
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_SHIFT 0
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_MASK 0x00000003U
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB(v) \
        ((v) << NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_MASK) | ((v) << NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_SHIFT))
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_MASK) >> NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_SHIFT)
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE0_MSB_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1_SHIFT 2
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1_MASK 0x000000fcU
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1(v) \
        ((v) << NDP120_DNN_ISA_COMP7_PADDING_SIZE1_SHIFT)
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP7_PADDING_SIZE1_SHIFT))
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP7_PADDING_SIZE1_MASK) | ((v) << NDP120_DNN_ISA_COMP7_PADDING_SIZE1_SHIFT))
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP7_PADDING_SIZE1_MASK) >> NDP120_DNN_ISA_COMP7_PADDING_SIZE1_SHIFT)
#define NDP120_DNN_ISA_COMP7_PADDING_SIZE1_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0_SHIFT 8
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0_MASK 0x000fff00U
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0(v) \
        ((v) << NDP120_DNN_ISA_COMP7_CENTER_COORD0_SHIFT)
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP7_CENTER_COORD0_SHIFT))
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP7_CENTER_COORD0_MASK) | ((v) << NDP120_DNN_ISA_COMP7_CENTER_COORD0_SHIFT))
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP7_CENTER_COORD0_MASK) >> NDP120_DNN_ISA_COMP7_CENTER_COORD0_SHIFT)
#define NDP120_DNN_ISA_COMP7_CENTER_COORD0_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1_SHIFT 20
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1_MASK 0xfff00000U
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1(v) \
        ((v) << NDP120_DNN_ISA_COMP7_CENTER_COORD1_SHIFT)
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_ISA_COMP7_CENTER_COORD1_SHIFT))
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_ISA_COMP7_CENTER_COORD1_MASK) | ((v) << NDP120_DNN_ISA_COMP7_CENTER_COORD1_SHIFT))
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1_EXTRACT(x) \
        (((x) & NDP120_DNN_ISA_COMP7_CENTER_COORD1_MASK) >> NDP120_DNN_ISA_COMP7_CENTER_COORD1_SHIFT)
#define NDP120_DNN_ISA_COMP7_CENTER_COORD1_DEFAULT 0x00000000U
#define NDP120_DNN_ISA_COMP7_DEFAULT 0x00000000U 

#endif
